The present invention relates to electronic systems and, more specifically, to electronic and data processing systems constructed using all-metal circuit components. Still more specifically, the present invention provides techniques for constructing all-metal, three-dimensional circuits in which circuit components are stacked on top of one another.
Semiconductor technology provides the foundation of practically all electronic systems. The device density of silicon technology has increased steadily in the decades since its introduction and, until recently, roughly conformed to Moore's law which states that the device density of silicon chips doubles every eighteen months. That is, in recent years, the rate at which the bit density of silicon memories has improved has increasingly fallen short of the rate predicted by Moore's law. The limitations of semiconductor technology are readily apparent in the widening gap between its future potential and its past performance. There are a number of reasons for this.
In spite of the fact that the finer manufacturing geometry is aimed at offsetting the area increase brought about by the doubling of the transistor number, in practical terms the increase in number of transistors has increased the silicon area and the manufacturing costs.
The basic building element of semiconductor-based electronic components is the transistor. The quality of a transistor is directly determined by, among other factors, the perfection of the crystalline substrate structure used to manufacture it. Using currently available techniques, integrated circuits, which are collections of multiple interconnected transistors, can be reliably assembled only as “planar” or 2D structures because transistors can be built only on the top surface of a crystalline silicon wafer. Attempts to deposit silicon atoms, organized in perfect crystalline patterns, on top of an oxide, metal layer, or other layers have been unsuccessful thus far. Technology advances such as polycrystalline silicon structures and chemical-mechanical polishing have been utilized to build inferior quality transistors with reduced performance and increased dimensions.
In addition, improvements in transistor performance are limited by physical and process technology constraints. For example, as the feature size of silicon devices shrinks, undesirable effects occur including the loss of information through charge leakage, high oxide breakdown, and power consumption problems. Inherent limitations such as the non-scalability of p-n junctions and charge pumps also translates into an inability to take full advantage of advances in lithography.
Memory systems which incorporate mechanical elements, e.g., disk drives, are also facing technological obstacles relating to storage density such as, for example, the difficulty of mechanically aligning a read head with increasingly smaller storage locations on a magnetic storage medium. Access times for such memories are also typically orders of magnitude greater than that of the semiconductor memories which they complement. Such memories are also vulnerable to a variety of environmental stresses including, for example, shock, vibration, temperature extremes, radiation, etc. In combination, such limitations impede the dual objectives of greater information density and faster information access.
The evolution of memory technologies such as FLASH and EEPROM have addressed some of these limitations in that they have much faster access time than conventional magnetic memories and are more resistant to some environmental stresses, e.g., mechanical shock. However, these “hardcard” technologies do not have sufficient storage density or capacity to support the average stand-alone or networked computer system. Indeed, with a fraction of the capacity of standard disks, FLASH and EEPROM provide only supplemental storage capacity and have the added disadvantage of a limited number of access cycles. Moreover, although FLASH and EEPROM access times are better than those of conventional mechanical systems, they are clearly inferior as compared to DRAM or SRAM access times. In addition, the high power consumption per megabyte associated with FLASH and EEPROM necessitates larger power supplies, obviating the hardcard technologies' advantage in size and weight. Therefore, although FLASH and EEPROM provide advantages with regard to speed and reliability, these memory technologies cannot achieve the capacity or endurance of conventional magnetic disk drives.
In view of the foregoing, it is desirable to provide alternatives to conventional semiconductor technologies for building electronic systems.